A. Field of the Invention
This invention relates to an improved control system for controlling the pipelined execution of different types of instructions in a digital data processing system. More particularly, it relates to a control system providing dual pipeline control consisting of hardware generated control signals for execution of standard machine instructions and microcode generated control signals for execution of complex or extended cycle machine instructions. Still more particularly, an additional feature of the invention provides a second microcode controller for localized control of the execution of certain decimal instructions within the pipelined instruction execution system.
B. State of the Prior Art
In many prior art general purpose computers, instructions are executed in a sequential manner from one instruction to the next, unless the instruction flow is modified by a branch condition or otherwise. In general, the operations performed to execute the instruction after it is fetched from storage can be described functional as follows:
1. Decode the instruction and generate the address of any operands required by the instruction; PA1 2. Fetch the operands from memory if so specified; and PA1 3. Perform the operation defined by the instruction and store the results in memory. PA1 1. Operand Cache Read/Write Controls PA1 2. Operand Address Generations PA1 3. Arithmetic Control Fields PA1 4. Instruction Pipeline Sequencing PA1 5. Initial IP Start-up Control PA1 6. Interrupt Initiation and Reporting PA1 7. Abort/Wait/Halt Control
A primary goal in designing computer architecture is to increase the speed at which instructions may be executed. One commonly used technique to increase speed is pipelining of instructions. Pipeline execution is much like assembly of an item in assembly line operation where various required operations are performed at different stages and locations as the item moves down the assembly line. Pipelined instructions enter and exit the pipeline at intervals that are shorter than the time it takes to process a single instruction. This is accomplished by dividing the process of instruction execution into stages which correspond to the different functional operations which must be performed. Typically, these functional operations are divided so that each may be completed within one timing cycle of the system. In that case the pipeline stages correspond directly to the system timing cycles such that one pipeline stage is completed every timing cycle. Each of the functional operations are processed by a different stage of the pipeline. It may be considered that the instruction "travels" from one stage of the pipeline to the next at fixed times. Each stage of the pipeline performs part of the instruction execution. For example, the data processing system of this invention utilizes a three stage pipeline divided into the functional stages set forth above. In fully pipelined operation, instructions are overlapped such that each stage of the pipeline is processing a separate instruction at the same time. Even though each instruction requires three stages to process, because of overlapped operation, one instruction completes every stage. Therefore, it is evident that proper operational control of the instruction execution pipeline is essential to the optimal operation of the system.
Two types of control systems are generally known and used. These are hardwired logic control systems (hardware) and microcode control systems. Each type offers both advantages and disadvantages. Hardware controlled systems utilize combinatorial logic circuitry and some state registers to decode machine instructions in order to produce control signals. Such systems are noted for their high speed, low power consumption and minimal circuit size. They require considerable time to initially develop and perfect, and are costly to initially produce. Hardware control systems are developed for specific instruction sets and are very difficult to change or modify in order to adapt to new instructions or to enhancements of old instructions or to correct system deficiencies. Additionally, if the instruction set contains complex instructions, the amount of time involved in design and perfection of the logic circuitry increases as well as the amount of hardware which is needed.
Microcode controlled systems utilize information contained in the machine instruction to identify the starting address of a sequence of microinstructions to develop control signals to control logic used in executing the machine instructions. The microinstructions for the machine instruction execution are initially programmed and stored in a microcode program memory. Consequently, a substantial advantage of microcode controlled systems is the relative ease with which they can be initially designed and set up. Additionally, when compared to hardware controllers, microcode controllers take considerably less effort or expense to modify in order to correct system deficiencies or to adapt the system to new instructions or changes in old instructions. Unfortunately, microcode controllers are not as fast as hardware controllers and typically use more power and space. Thus, it would be advantageous to have a control system which incorporates the advantages found in both hardware and microcode control systems while at the same time eliminating, or at least minimizing, the disadvantages.
Numerous different types of control systems are known for controlling digital data processing systems. Each of these systems may be categorized as either microcode controlled systems or hardware controlled systems. These systems are continually undergoing change and modifications in order to improve their efficiency to optimize system operation. One of the methods known and used to improve the performance of microcode controlled systems is to incorporate certain hardware circuitry to generate additional control signals. For example, U.S. Pat. No. 4,761,755 to Ardini, Jr. et al., discloses a microcode controlled data processing system having instruction responsive control hardware for generating control signals used in configuring the arithmetic logic unit and for controlling data string manipulation circuitry. Similarly, U.S. Pat. No. 3,872,447 to Tessera et al, discloses a microcode controlled system having a hardwired sequencer which, in response to the same address bits used to address the microcode control store, provides additional control signals. In both of these prior art systems the additional hardware control signals are used to supplement to the primary control signals provided by microcode in order to control certain limited functional areas during instruction execution. At all times, however, instruction execution and sequencing remains under microcode control.
In contrast to these prior art control systems, the present invention provides a dual control system which functions as a hardware controller during the execution of standard instructions and as a microcode controller during the execution of complex or extended cycle instructions. In this manner the dual control system is able to provide the speed of hardware control for execution of standard instructions and the flexibility of microcode control desirable for complex or extended cycle instructions.